Cortex-A53

Major features of the LS1043 implementation:

Design Parameter Value
ISA Version ARMv8.0
Cores 4
L1 ICache 32K with ECC protection
L1 DCache 32K with ECC protection
L2 Cache Size 1024K (shared between all cores) with ECC protection
L2 data RAM input latency 1 cycle
L2 data RAM output latency 2 cycles
SCU L2 cache protection Yes
SIMD (Neon) Yes
Double-Precision floating point Yes
Cryptography extension Yes
CPU cache protection Yes
Execution In-order
Virtualization Yes
Cache protection Yes

Note Not all of these parameters (i.e cache sizes, latency) are the same across all Cortex-A53 implementations.

For example, the A53 cluster in the Raspberry Pi 3 has 512K of L2 cache vs 1024K on the LS1043.