Data Path Acceleration Architecture
The Data Path Acceleration Architecture (DPAA) block is responsible for Ethernet functions on the LS1043, as well as some cryptography acceleration functions
DPAA consists of several blocks:
- Queue manager (QMan)
- Frame manager (FMan)
- Buffer manager (BMan)
- Security engine (SEC)
Compared to the descriptor-ring based Ethernet controllers in many SoC's, DPAA maximizes the use of multi-core processors by distributing the packet flows across all cores.
DPAA is not a 'flow accelerator' that is seen in many residential router SoC's, but does have some limited offloading features for certain usecases (such as IPSec).
Packet flows in DPAA can be customised in various ways, the scope of which is out of scope for this guide.
For more information we recommend:
Section 5 of NXP app note AN5079. While this document refers to the previous generation PowerPC processors, the concepts are the same.
Freescale presentation APF-SNT-T1719 also contains some notes about FMan,Bman and Qman as it pertains to the LS1043.
Freescale presentation FTF-NET-F0146 provides a general overview of DPAA.
Freescale presentation FTF-NET-F0111 describes the IPSec offload capabilities in DPAA as well as providing a brief overview of DPAA1.
Documentation/networking/dpaa.txt in the Linux kernel tree
Note DPAA version 1 (in LS1043, LS1046, QorIQ T Series) is not the same as DPAA version 2 (LS1088,LS2088).
Some high end SoC's have extra functionality (pattern matching, compression, RapidIO) which is not present in the LS1043.
FMan requires microcode to function, this is normally loaded by u-boot. This can be obtained from NXP's GitHub.
The microcode source is not generally available to those outside of NXP.