Highly Anticipated and/or Frequently Asked Questions
Why are there no (native) SATA ports? The LS1043 has SATA inside?
There is no SerDes configuration that supports both 10G (XFI) and SATA. If you are adventurous, you can change the RCW to disable the 10G and run SATA on Lane D (the half-height mPCIe slot).
Connecting a SATA port in this manner is an exercise for the reader (and not supported!).
What is the maximum MTU size supported on the LS1043?
In some previous kernel versions, this was 4000 bytes due to Errata A-010022.
Full 9.6K jumbo frames should work after this patch.
What are the operational limits, with regards to power and temperature?
System will be halted (by the thermal sensor EMC1703/U45 and STM8S U5) when the board temperature reaches 80C, this is the maximum rated temperature of the DDR4 RAM parts, among others. The power LED will turn RED if this occurs.
If this is bypassed, the qoriq-thermal driver shuts down the CPU at 100C (at this operating point, a CPU<->Board difference of 20-25C is typical).
The external reset is on header P1 (next to the RTC battery), with a 100K pullup to 3.3V. Driving pin 1 to GND (pin 2) will trigger a CPU reset.
Is there a 'Management Engine' (cf. Intel CPUs)
No :) The CPU executes the code from the defined boot/RCW/PBL source (NAND or SD) and nothing else.
It is possible to execute code above the operating system using TrustZone/Protected Primary Applications, which would typically be used to provide assurance in Secure Boot applications. Traverse does not ship any retail boards with such a setup, nor do we program any secure boot keys or settings except when requested by OEM customers.
Is VFIO/PCIe pass through to KVM supported?
No. As far as we are aware, this is not possible on systems using the GICv2/GIC-400 interrupt controller, such as the LS1043.
Future products with newer system on chips may support this.
Firmware and flash
What firmware blobs are required?
Frame Manager (FMan) microcode – required to use all on board network ports. Get it here: https://github.com/NXP/qoriq-fm-ucode
These firmwares are loaded by u-boot or TianoCore, i.e your operating system image does not need to include them.
Some LS1043 models require QUICC Engine (QE) microcode. This feature is not exposed on the LS1043-S board and loading the QE firmware is not required.
I am running a standard Linux distribution and/or mainline kernel. Why do the network interfaces stop working shortly after boot?
We have discovered an issue with irqbalance and the mainline DPAA driver.
If the QMan interrupts are reassigned from their original cores, DPAA will stop working.
To resolve this issue, disable the irqbalance service.
I wiped my NAND flash and now EFI-based distributions will not boot!
Check that you have added both the PPA firmware (see above) and device tree (DTB) blobs, without these it is not possible to boot an EFI distro.
Hardware Hacking and Debugging
Is the source code for the STM8S available?
Yes, to volume/OEM customers. Please contact us for more information.
What is the JTAG pinout?
The standard ARM 10 pin 1.27mm pitch pinout.